8051 Interrupt Programming explores the mechanisms of interrupt handling in the 8051 microcontroller. It details the types of interrupts, including timer and external hardware interrupts, and explains how to enable and disable them using the Interrupt Enable (IE) register. This unit is essential for students and engineers working with embedded systems, providing practical insights into interrupt service routines (ISRs) and their applications. The content is designed for those studying microcontrollers and aims to enhance understanding of real-time system responses.

Key Points

  • Explains the concept of interrupts in the 8051 microcontroller and their significance.
  • Describes how to enable and disable interrupts using the Interrupt Enable (IE) register.
  • Covers types of interrupts including timer interrupts and external hardware interrupts.
  • Details the structure and function of interrupt service routines (ISRs).
  • Includes practical examples of interrupt handling in embedded systems.
PRAGADHI R
6 pages
Language:English
Type:Lecture Notes
Biology
PRAGADHI R
6 pages
Language:English
Type:Lecture Notes
Biology
PRAGADHI R
6 pages
Language:English
Type:Lecture Notes
Biology
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8051 Interrupt Programming – Unit 4 pdf

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ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY
EC8691 MICROPROCESSORS AND MICROCONTROLLERS
5.3 INTERRUPT PROGRAMMING IN 8051
The Microcontroller can serve several devices. The Interrupt is the method to
indicate the microcontroller by sending an interrupt signal. After receiving an interrupt,
the microcontroller interrupts whatever it is doing and serves the device. The program
associated with the interrupt is called the interrupt service routine (ISR). When an
interrupt is invoked, the microcontroller runs the interrupt service routine. For every
interrupt, there is a fixed location set aside to hold the addresses of ISRs.
The following events will cause an interrupt:
1. Timer 0 Overflow.
2. Timer 1 Overflow.
3. Reception/Transmission of Serial Character.
4. External Event 0.
5. External Event 1.
To distinguish between various interrupts and executing different code depending on
what interrupt was triggered, 8051may be jumping to a fixed address when a given
interrupt occurs as shown in Table 5.3.1.
Table 5.3.1 Interrupt Vector Table for 8051
[Source: “The 8051Microcontroller and Embedded Systems: Using Assembly and C” by Mohamed Ali Mazidi,
Janice Gillispie Mazidi, Rolin McKinlay, pg.no.320]
ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY
EC8691 MICROPROCESSORS AND MICROCONTROLLERS
ENABLING AND DISABLING AN INTERRUPT
Upon reset all interrupts are disable, meaning that known will be responded to by
the microcontroller if they are activated. The Interrupt must be enabled by software in
order for microcontroller to respond to them there is a register called IE that is responsible
for enabling and disabling the interrupts as shown in Figure 5.3.1
Figure 5.3.1 Interrupt Enable(IE) Register
[Source: “The 8051Microcontroller and Embedded Systems: Using Assembly and C” by Mohamed Ali Mazidi,
Janice Gillispie Mazidi, Rolin McKinlay, pg.no.321]
PROGRAMMING EXTERNAL HARDWARE INTERRUPTS
The 8051 has two external hardware interrupts PIN 12 (P3.2) and Pin 13 (P3.3),
designated as INT0 and INT1. Upon activation of these pins, the 8051 finishes the
ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY
EC8691 MICROPROCESSORS AND MICROCONTROLLERS
execution of current instruction whatever it is executing and jumps to the vector table to
perform the interrupt service routine.
TYPES OF INTERRUPT
1)Level-TriggeredInterrupt
2)Edge -Triggered Interrupt
LEVEL-TRIGGERED INTERRUPT
In this mode, INT0 and INT1 are normally high and if the low level signal is
applied to them, it triggers the Interrupt. Then the microcontroller stops and jumps to the
interrupt vector table to service that interrupt. The low-level signal at the INT pin must
be removed before the execution of the last instruction of the ISR, RETI. Otherwise,
another interrupt will be generated. This is called a level-triggered or level-activated
interruptandis the default mode upon reset
Figure 5.3.2 Activation of INT0 and INT1
[Source: “The 8051Microcontroller and Embedded Systems: Using Assembly and C” by Mohamed Ali Mazidi,
Janice Gillispie Mazidi, Rolin McKinlay, pg.no.326]
EDGE -TRIGGERED INTERRUPT
Upon reset 8051 makes INT0 and INT1 low l Level-Triggered Interrupt. To make
them Edge -Triggered Interrupt, we must program the bits of the TCON Register. The
TCON register holds among other bits and IT0 and IT1 flags bit the determine level- or
edge triggered mode. IT0 and IT1 are bits D0 (TCON.0) and D2(TCON.2) of the TCON
Register respectively.
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End of Document
241

Figures

Interrupt Vector Table for 8051
Interrupt Enable(IE) Register
Activation of INT0 and INT1
Example for Level triggered Interrupt
Example for Serial Communication Interrupt
Example for Timer Interrupt

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FAQs

What are the types of interrupts in the 8051 microcontroller?
The 8051 microcontroller has two main types of interrupts: Level-Triggered Interrupts and Edge-Triggered Interrupts. Level-Triggered Interrupts occur when a low-level signal is applied to the INT pins, INT0 and INT1, which must be removed before the ISR's last instruction, RETI, to prevent additional interrupts. Edge-Triggered Interrupts, on the other hand, require programming the TCON register to configure the INT pins to respond to changes in signal rather than levels.
How does the 8051 handle serial communication interrupts?
In the 8051 microcontroller, serial communication interrupts are managed through two flags: TI (Transfer Interrupt) and RI (Received Interrupt). TI is raised when the stop bit is transferred, indicating that the SBUF register is ready for the next byte. Conversely, RI is raised when the stop bit is received, signaling that the received byte must be processed before it is lost due to new incoming data. The ISR for serial communication checks these flags to determine the cause of the interrupt.
What is the role of the Interrupt Enable (IE) register in the 8051?
The Interrupt Enable (IE) register in the 8051 microcontroller is crucial for managing interrupt responses. Upon reset, all interrupts are disabled, meaning the microcontroller will not respond to any activated interrupts. To enable specific interrupts, the IE register must be configured accordingly. This register contains bits that control the enabling and disabling of various interrupts, allowing the microcontroller to respond to external events and timers appropriately.
What happens when an external hardware interrupt is triggered in the 8051?
When an external hardware interrupt is triggered on pins INT0 (P3.2) and INT1 (P3.3) of the 8051 microcontroller, the device completes the execution of the current instruction and then jumps to the interrupt vector table. This action allows the microcontroller to service the interrupt by executing the corresponding Interrupt Service Routine (ISR). The ISR is crucial for handling events from external sources, ensuring timely responses to hardware signals.
What is the significance of the Timer Interrupt in the 8051?
The Timer Interrupt in the 8051 microcontroller is significant for managing timing events without holding up the microcontroller's operations. When the timer rolls over, the timer flag (TF) is raised. If the timer interrupt is enabled in the IE register, the microcontroller will be interrupted regardless of its current task, allowing it to jump to the ISR for the timer. This mechanism enables the microcontroller to perform other tasks until it is notified that the timer has rolled over, improving efficiency.

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