
8085 Microprocessor Page 3
IO/M: It is a signal which is used to distinguish
between IO operation and memory operation. It is
also used in generating memory and IO, read and
write control signals.
S1, S0: These are status signals. Depending on the
value on these lines, the type of operation being
performed by the processor can be determined.
Below table shows that information.
Power Supply and clock signals:
Vcc: +5v power supply line
Vss: Electrical ground signal.
X1, X2: Crystal is connected between these pins. The frequency is internally divided by 2.
The systems operates generally at 3MHz. Hence 6 MHz clock signal needs to be connected
between X1, X2 lines.
CLK (out): It is the clock output signal from processor, which can be used to clock other
peripherals in the microprocessor based system.
READY: This is used when the processor is reading or writing data to a slow peripheral.
When this signal goes low processor inserts wait states, until it goes high.
Reset Signals:
RESET IN: When low signal is applied on this pin, 8085 resets and the microprocessor
boots from 0000h location in memory i.e. PC is loaded with 0000h location.
RESET OUT: When processor is reset, this signal goes high. This pin is connected to reset
input of other peripherals. So when processor is reset, other peripherals are also reset.
Serial IO lines:
SID: serial input data, used to receive serial data.
SOD: serial output data, used to send serial data
Interrupt Signals:
INTR: interrupt request is general purpose interrupt signal. The interrupting device needs
to send the vector address also.
INTA: is interrupt acknowledging signal. This signal indicates that processor has accepted
the interrupt.
RST7.5, RST6.5, RST5.5: These are external vectored interrupts. When these interrupt
occurs, processor vectors to a specific location.
TRAP: It is a non-mask able interrupt.
DMA signals:
HOLD: This line is used by DMA controller to request microprocessor for system bus.
When this line goes high microprocessor completes its current bus cycle and issues system
bus to DMA controller.
HLDA: HOLD acknowledging signal. Processor acknowledges DMA request using this signal.