BIT103 Digital Logic focuses on essential concepts in digital logic design, including BCD-to-seven segment decoders, flip-flops, and sequential circuits. This resource is tailored for first-year Bachelor of Information Technology students at Tribhuvan University. It covers both long and short answer questions, providing a comprehensive overview of digital logic principles. The document also includes practical exercises for converting number systems and designing counters, making it a valuable study aid for students preparing for exams.

Key Points

  • Covers BCD-to-seven segment decoder design for decimal numbers.
  • Explains the operation and characteristics of JK flip-flops.
  • Includes exercises on converting number systems and performing binary subtraction.
  • Provides a design guide for synchronous counters using T-flip flops.
Sewang Rai.2
1 page
Language:English
Type:Past Paper
Computer Science
Sewang Rai.2
1 page
Language:English
Type:Past Paper
Computer Science
172
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BIT103-2079 ✡
Tribhuvan University
Institute of Science and Technology
2079
✡
Bachelor Level/First Year/First Semester/Science Full Marks: 60
Bachelors in Information Technology (BIT 103) Pass Marks: 24
(Digital Logic) Time: 3 hours
Candidates are required to give their answers in their own words as for as practicable.
The figures in the margin indicate full marks.
Section A
Long Answer Questions
Attempt any TWO questions. [2 10=20]
×
1. Design a BCD-to Seven-segment decoder to display decimal numbers 1, 2 and 4. [10]
2. What are the drawbacks of clocked RS flip flop? Explain the operation of a JK flip flop along
with its characteristic table, characteristic equation circuit diagram and timing diagram.
[2+8]
3. Design a sequential circuit using JK flip-flop with the help of given state diagram. [10]
Section B
Short Answer Questions
Attempt any EIGHT questions. [8 5=40]
×
4. Convert (110.101)
8
into binary and decimal number system. [2.5+2.5]
5. Subtract (739.57)
10
— (78.35)
2
using both 10's and 9's complement. [2.5+2.5]
6. What is magnitude comparator? Design 2-bit magnitude comparator. [1 + 4]
7. Define Half-subtractor with truth table and logic diagram. [5]
8. What is decoder? Implement 8 1 MUX using 2 1 MUX. [1+4]
× ×
9. Design and explain the operational characteristics of D-flip flop. [5]
10. Design Mod-5 synchronous counter using T- flip flop. [5]
11. Draw a Serial-In Serial-Out Shift register and explain it. [5]
12. Write short notes on: (Any two) [2.5 2=5]
×
a. BCD code
b. Status Register
c. Ring Counuter
IOST, TU
BIT103 - Digital Logic - Board 2079 - bitinfoNepal
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End of Document
172

Figures

Section B

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FAQs

What is a BCD-to-Seven-segment decoder and how is it designed?
A BCD-to-Seven-segment decoder is a digital circuit that converts Binary-Coded Decimal (BCD) inputs into outputs that can drive a seven-segment display. To design one for displaying decimal numbers 1, 2, and 4, one must create a truth table that maps the BCD inputs to the corresponding segments of the display. The design involves determining which segments need to be activated for each decimal number and implementing the logic using basic gates.
What are the drawbacks of clocked RS flip-flops?
Clocked RS flip-flops have several drawbacks, including the potential for indeterminate states and race conditions when inputs change simultaneously. This can lead to unpredictable behavior in sequential circuits. In contrast, JK flip-flops address these issues by allowing for more stable operation, as they can toggle states based on the inputs, thus providing a more reliable performance in digital systems.
How do you implement an 8 × 1 multiplexer using 2 × 1 multiplexers?
To implement an 8 × 1 multiplexer using 2 × 1 multiplexers, you can cascade multiple 2 × 1 MUXes. Start by using four 2 × 1 MUXes to select from the eight inputs, combining them into two outputs. Then, use another two 2 × 1 MUXes to select between these outputs. Finally, a single 2 × 1 MUX can be used to choose the final output from the last two outputs, effectively creating an 8 × 1 MUX configuration.
What is a magnitude comparator and how is a 2-bit comparator designed?
A magnitude comparator is a digital circuit that compares two binary numbers and determines their relative magnitudes. To design a 2-bit magnitude comparator, you can use basic logic gates to create a truth table that outlines the conditions for equality, greater than, and less than. The circuit will output signals indicating whether one number is greater than, less than, or equal to the other based on the input bits.
What is a half-subtractor and what is its truth table?
A half-subtractor is a combinational circuit that performs the subtraction of two bits, producing a difference and a borrow output. The truth table for a half-subtractor includes inputs A and B, with the outputs being the difference (A-B) and borrow. The difference is 1 when A is greater than B, and the borrow is 1 when B is greater than A. The logic diagram typically consists of XOR and AND gates to achieve these outputs.
What is a D-flip flop and what are its operational characteristics?
A D-flip flop is a type of digital memory circuit that captures the value of the input data (D) at a specific clock edge and holds it until the next clock edge. Its operational characteristics include a single data input, a clock input, and outputs that reflect the stored value. The D-flip flop is widely used in registers and memory devices due to its simplicity and effectiveness in storing binary information.
How is a Mod-5 synchronous counter designed using T-flip flops?
To design a Mod-5 synchronous counter using T-flip flops, you need to configure the T-flip flops to toggle based on certain conditions derived from the counter's state. The design involves setting up the flip-flops in a way that they count from 0 to 4 and then reset back to 0. The counter will require additional combinational logic to ensure it resets after reaching the count of 5, thus achieving the desired Mod-5 operation.

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